A. Field of the Invention
The present invention relates to automatic testing of electronic circuits, and more particularly to improved interconnect testing techniques for circuit boards containing both boundary-scan and non-boundary-scan devices.
B. Description of the Related Art
The complexity of digital devices and intricacy of typical circuit boards containing such devices has resulted in the development of a variety of electronic test instruments that examine the boards or the devices themselves for defects. The type of test that is appropriate for a particular situation depends on the functions performed by the board, the relative costs of the various components thereon, and the degree to which such components are physically accessible to the test equipment.
For example, an entire board might be subjected to a "functional" test that verifies proper operation in response to certain types of input, as well as "interconnect" testing to assess the integrity of connections between components. Particular devices can also be individually tested "in-circuit", i.e., without being physically disconnected from the board. The latter approach permits the manufacturer to salvage the remainder of the board, replacing only the device(s) found to be defective.
Testers that perform interconnect and in-circuit testing typically operate by applying electrical signals to points on the board along electrical connections, or "nodes", to the device or pathways to be tested. A conventional tester includes digital drivers and scanners for generating and sensing logic signals. A test fixture (such as the well-known "bed-of-nails" fixture) configured to connect the drivers and sensors to the board's conductive tracks can be used to introduce electrical signals at these or other physically accessible points and read voltage levels at others. In the case of an interconnect test, the sensed signals enable the tester to determine whether electrical continuity properly or improperly exists between the driven and sensed points.
As the complexity of a board increases, the need for physical access to the driving and sensing points usually restricts the number of tests that may be performed. To alleviate such access requirements, device manufacturers have designed components that include so-called scan circuitry in addition to the circuitry required for the normal operation of the component. The scan facility enables such components to switch from ordinary operation into a "scan" mode used for testing.
The scan circuitry comprises a plurality of cells that are operative in the scan mode. The cells are connected together in a shift-register configuration such that data can be loaded into the cells serially from a single scan input terminal and the contents of the cells can be read serially from a single scan output terminal. Each cell is associated with a different (and possibly hard-to-access) node in the component. The shift register can be commanded to cause its component cells to "capture" the states of their associated nodes, and the states of those nodes at the time of the command can then be observed by advancing the resultant contents along the shift register to the scan output terminal. This facility enables a tester to take a "snapshot" of the signals at nodes to which physical access would otherwise be difficult or impossible.
The scan facility can be used for driving the associated nodes as well as sensing them: the shift register can be commanded to cause the component cells to apply to their respective nodes signals representing contents that have been serially loaded into those cells by advancement along the shift register from the scan input port.
One type of scan organization is known as "boundary" scan because the nodes with which the cells are associated are respective ones of the input and output terminals used in normal component operations; the nodes are thus in a sense on the "boundary" of the device. The cells can be thought of as being interposed between the terminals and the internal component logic but transparent during normal operation. When such components have been switched from normal operation to the scan mode, the cells not only can be loaded and read serially but can also be caused both to receive and to transmit data in parallel.
Specifically, cells associated with output terminals can be caused either to accept the values represented by the signals that the component's internal circuitry would otherwise place on the output terminals, or to place on the output terminals either these values or selected cell contents that have previously been loaded by advancement along the scan shift register. Cells associated with input terminals can be caused either to load in the values represented by the signals received at their respective terminals from external sources, or to apply either these signals or values serially loaded along the scan shift register to the internal nodes with which their respective terminals communicate.
Boundary-scan components can be linked together at the device level, with the scan output terminal of one component in the chain coupled to the scan input terminal of the next component in the chain. The entire set of linked components, referred to as a "scan path", then behaves as a "super" shift register in response to the data stream. The process of shifting data into the boundary-scan cells is hereinafter referred to as "scanning in". This operation necessarily results in shifting the existing data out of these same cells, a process hereinafter referred to as "scanning out". By using the boundary-scan facility, one can effectively apply and sense signals at all scan-component terminals by direct physical access only to the scan input terminal of one component and the scan output terminal of another.
The details of a standard approach to boundary-scan operation are described in IEEE Standard 1149.1-1990 (hereinafter "IEEE 1149.1"), which sets forth a set of accepted operational parameters and definitions for boundary-scan components.
By using a boundary-scan arrangement, it is possible to perform a number of tests with a minimum number of physical connections between the test system and the board or device. The devices can themselves be tested for internal integrity by setting the boundary-scan input cells of each device in the scan path to predetermined logic states, transferring these states into the internal device elements for processing (as if these states had originated on each device's input terminals), capturing the post-processing output values on the output boundary-scan cells (which would ordinarily have been transferred to the device's output terminals), and examining the contents of the output cells to verify that each device has responded properly to its input. This type of inspection is called an "internal test" (and is triggered by an INTEST instruction in IEEE 1149.1).
In boards consisting exclusively of boundary-scan components, the boundary-scan facility can be used to test for short- or open-circuit conditions between devices. Such interconnect testing is ordinarily accomplished by performing an "external test", in which ordinary device functions are suspended and the boundary-scan cells used to determine device outputs and/or observe device inputs without allowing data to enter or emerge from the internal component logic. (The EXTEST instruction described in IEEE 1149.1 triggers capture of input-terminal states into the scan-path input cells and presentation on the output terminals of the logic states contained in the output cells.) One applies a voltage corresponding to the low or high logic state at a node which is ordinarily electrically connected to the input terminal, causes the corresponding boundary-scan cell to capture the state of this input terminal, and ascertains the state of the cell by scanning its value out; this process is repeated for the other logic state. Diagnostic conclusions can be drawn from analysis of the scanned-out data based on the electrical characteristics of the logic family under test. For example, since non-driven nodes in TTL circuits tend to drift to the non-dominant, high logic state, an open-circuit condition in a node can be inferred if the observed state of the cell corresponding to an input terminal on the node is high in response to application of both high and low logic states at an output terminal on the node.
A similar analysis can be used to detect short-circuit conditions. In principle, the only difference is that the driven and sensed points are ones that are not connected together in a good board. In practice, one may additionally drive not only the point that should not be connected to the sensed point but also, with the opposite logic level, one that should. Since a short circuit between drivers attempting to drive their (now common) output nodes to conflicting states results in that node's assumption of the level that is dominant for the particular logic family to which the components belong, one can infer a short-circuit condition if the same low response results from both driver logic levels.
It is desirable to test simultaneously for open circuits on a number of nodes, or for short circuits between numbers of pairs of nodes and this often requires that many nodes be driven simultaneously. When they are, a deviant result at one terminal can indicate that it is shorted to any one of many different other terminals. To enable the tester to identify the other terminal to which such a terminal is shorted, testers typically do not apply merely the simple two-bit sequence mentioned above. Instead, they apply relatively long sequences so that each terminal in a group of device output terminals can be assigned a different multi-bit "identifier" (hereinafter referred to as a "serial test vector" or "STV"), whose bits are applied to that terminal in sequence. Each set of corresponding (simultaneous) bits from all STVs is hereinafter referred to as a "parallel test vector" or "PTV". The first PTV bit is serially loaded into the output boundary-scan cells over the scan serial input terminal.
The bits of a single PTV are transferred in parallel to the output terminals of the associated devices (that is, the output terminals are set to voltage levels representative of the logic states of the cells), and the resultant states of all input terminals are then captured simultaneously into the input boundary-scan cells. The captured input is referred to as a "parallel response vector", or "PRV".
The contents of all boundary-scan cells are then scanned out, and the process is repeated for the next PRV. The PRV values expected of a good board for each PTV can be deduced from the known pattern of interconnections among devices. The sequence of PRVs defines a set of "serial response vectors", or "SRVs". If a short circuit is the cause of an input terminal's deviating from its correct SRV, the node to which that input terminal is shorted can often be identified by comparing the deviant SRV to the various identifier STVs.
Boundary-scan architecture reduces the burdens of testing by alleviating the need for physical access to components or board sites. This eliminates difficulties arising both from board topologies as well as tester multiplexing configuration.
Despite these advantages, boundary-scan architecture has not yet been widely adopted by suppliers of mass-produced ICs. Consequently, a significant number of circuit boards contain both boundary-scan components and non-scan components. The presence of the non-scan components, whose inputs and outputs cannot be controlled from the scan path, typically precludes straightforward application of the test strategies described above.
One of the reasons for this is that non-boundary-scan logic cannot be initialized reliably. Generating algorithms for initializing general sequential logic is difficult. Moreover, even if such algorithms can be generated, any of a variety of the as-yet unknown circuit faults could prevent successful implementation of such algorithms. The effect would be to make the results of the interconnect test unreliable and unrepeatable; that is, running the test twice on the same faults might produce different diagnoses.
On boards that contain conventional components exclusively, one generally performs interconnect tests with the board "dead," i.e., without power applied to its components, which therefore remain inactive during the test. Because the components generally remain inactive, they produce little or no interference with the test signals. Of course, one can perform such a dead-board test on mixed boards, too. But such a test cannot take advantage of the scan facility, which requires power to operate. Such a test thus cannot test for interconnection between the physically inaccessible points to which the scan facility would otherwise afford access. Testing the interconnection on mixed boards therefore presents a significant problem if advantage is to be taken of the scan facility.